philpem.me.uk Planar EL160.80.38-SM1 EL display  

Planar EL160.80.38-SM1 EL display

Introduction

This display is a 160x80 pixel monochrome (amber and black) display with a 6x3-pad matrix touch screen and three LEDs (two green, one amber). It includes an Epson SED1335 controller, and an ASIC which controls the touch screen and appears to perform some signal conversion work on the SED1335 timing outputs.

This display carries the following labels:

  • PART # 996-0277-01
    EL160.80.38-SM1
    REV: E

  • SUN PART NUMBER
    370-2311-02 REV: 50

  • PLANAR AMERICA
    MADE IN USA

The display has an 8-bit 8080-style data bus with two address lines. The LEDs are controlled by three pins on the connector and require external 680-ohm pull-up resistors. Two power supplies are required: +5V DC for the logic, and +12V DC for the analog circuitry (high-voltage power supply).

Different versions of the display

There appear to be at least two different versions of this display floating around. One uses a Xilinx XC3000-series FPGA to drive the touch panel, the other uses an ASIC, apparently custom-made for Planar by AMI (now AMIS).

The key difference between the two controllers is in the way that interrupts are handled. When a touchscreen event is detected, the Xilinx chip will pulse /INT low for around 15 to 20 nanoseconds, whilst the AMI chip will hold /INT low until the touch screen register is read from or written to. See below (under "Touch screen") for more information about this 'quirk'.

Input connector

The data connector is a 32-pin Hirose FX2. The connector on the board is Hirose part number FX2-32P-1.2SV(71), and the mating connector is P/N FX2-32S-1.27SV(71). Pin one is the top-right pin, pin two is directly below that (on the bottom right), pin 31 is on the top left and pin 32 is on the bottom right.

Unfortunately the FX2 isn't stocked by the likes of Farnell or Rapid, which makes it difficult to actually connect a cable to this display. It should be possible to find a connector with a similar footprint, though the sticking point is the distance between the bottom of the display PCB and the metal frame. The FX2 has a mated height of around 12mm.

The Samtec FTSH series pin header and FLE series socket may be suitable, although the mated height of these would only be 5mm or so (possibly less than that). An FTSH mated to a CLP would probably be even shorter. These would have to be cut to size (the 32-way size isn't a standard Farnell stock item, nor is the 30-way; the 40-way headers and receptacles could be cut down quite easily).

The Tyco-AMP AMPMODU connectors are another possible alternative; these are similarly priced, but have the option of a higher mated height (9.91mm for the 5-104693-3 header/plug, plus the 2.46mm base height of the 5-104652-3 receptacle/socket, for a total of around 12.5mm). The catch is that, once again, these aren't available in a 32-pin variant; the nearest size is 30 pins (which would work but the two ground pins would be left 'floating').

Additionally, there are two metal mounting tabs on the bottom of the AMPMODU connectors. Either holes would have to be drilled in the PCB (bad idea), or the tabs would have to be cut off. Removing the tabs would make the connector less rugged, though the metal frame would most likely provide plenty of support.

Pin configuration

Pin Name Function
1 LEDG1_L Cathode of bottom LED (green)
2 LEDY_L Cathode of middle LED (amber)
3 SELFTEST L=normal operation, H=self test
4 LEDG2_L Cathode of top LED (green)
5 A1 Address 1 (MSB)
6 GND
7 GND
8 A0 Address 0 (LSB). SED1335 /CS.
9 /RESET L=Controller reset
10 GND
11 D7 Data I/O 7 (MSB)
12 /WR L=Write
13 D6 Data I/O 6
14 GND
15 D5 Data I/O 5
16 /RD L=Read
17 D4 Data I/O 4
18 GND
19 D3 Data I/O 3
20 GND
21 D2 Data I/O 2
22 n.c. No connection
23 D1 Data I/O 1
24 GND
25 D0 Data I/O 0 (LSB)
26 /INT Interrupt output (AMI only?)
27 VL +5V (logic)
28 GND
29 VH +12V (analog)
30 VH +12V (analog)
31 GND
32 GND

The data bus should be pulled up to +5V using a resistor pack. I used 1k resistors, although 4k7 or 10k resistors (or anything in the range 1k to 10k) should be just as suitable. If you don't want to use the touchscreen, the data bus pull-ups may not be required.

Address map

A1 A0 Assigned to
0 0 SED1335
0 1 SED1335
1 0 Touch screen (column address)
1 1 Touch screen (row address)

Self test mode

If the SELFTEST pin is pulled low when the +5V and +12V supplies are connected, the display will function high. If it is pulled to +5V or left floating, however, the display will enter a self-test mode. Displays with the AMI ASIC will display an alternating all-pixels-on/all-pixels-off pattern, while boards with the Xilinx FPGA will display a pattern of vertical lines moving to the left.

The self-test is a good way to at least ensure that the power lines and grounds are wired up correctly, and that the display ASIC is at least partly functional (although I don't think the self-test tests the SED1335 controller).

SED1335 Initialisation

The following parameters are required to initialise the SED1335:

27x10-character layout with 6x8 characters

Command 0x40: System Set

M0      = 0 (internal CG ROM)
M1      = 0 (no D6 correction)
M2      = 0 (8-pixel character height)
WS      = 1 (dual panel drive)
IV      = 1
FX      = 5 (character width = 6)
FY      = 7 (character height = 8)
C/R     = 26 (27 columns of text)
TC/R    = 34 (26 + 8)
L/F     = 159 (80 rows, dual drive)
APH:APL = 32 (address increment)

20x10-character layout with 8x8 characters

This makes the math a little easier if you're doing graphics -- an entire byte is used for each block of 8 pixels (in 27x10 mode, a byte stores 6 pixels).

Command 0x40: System Set

M0      = 0 (internal CG ROM)
M1      = 0 (no D6 correction)
M2      = 0 (8-pixel character height)
WS      = 1 (dual panel drive)
IV      = 1
FX      = 7 (character width = 8)
FY      = 7 (character height = 8)
C/R     = 19 (20 columns of text)
TC/R    = 27 (19 + 8)
L/F     = 159 (80 rows, dual drive)
APH:APL = 32 (address increment)

Touch screen

This display incorporates a 6-row, 3-column 'pushbutton' type touch screen. The ASIC (either the Xilinx or AMI chip depending on display version) continuously scans the touchscreen, and stores the address of the pad which was touched (if any) in two registers -- ROW and COL.

The problem is that while the data is presented to the bus when /RD goes low, the touch screen registers (both of them!) are cleared on the low-to-high edge of /RD. To work around this, the procedure for reading the touch screen is:

  1. Set address pins to '10' (column address)
  2. Set data port to input mode
  3. /RD = 0 (start the read)
  4. Read the state of the data port -- this is the Column Address
  5. Set address pins to '11' (row address) without changing the state of /RD
  6. Read the state of the data port -- this is the Row Address

Now a little bit of extra processing has to be performed on the touch screen address in order to get an X/Y co-ordinate:

  1. AND the Column Address with 0x3F. This masks off the top two bits (which are always 1)
  2. AND the Row Address with 0x07. This masks off the top five bits.
  3. If Column == 0x3F or Row == 0x07, then the screen was not touched. Stop here.
  4. Column and row addresses are encoded as "one hot" bytes -- bytes with one bit set. To get the column address (in C):

    for (i=1; i<=8; i++) {
      if (column & 1) break;
      column >>= 1;
    }
    column = i;
    
  5. Repeat the above code block for the row address (replace 'column' with 'row').

You should now have two variables -- column and row -- which contain the column and row address of the touch. If there was no touch, then your function will have exited and returned nothing (I usually return 0xFF for the column and row addresses).

Touch screen interrupts

As mentioned above, there are (at least) two variants of the EL160.80.38-SM1 ASIC:

  • The AMI ASIC. Built by AMI for Planar, fully custom.
  • The Xilinx FPGA. A field-programmable gate array, with logic designed by Planar.

The key difference between the two is in how touch screen interrupts are handled. When a touch screen event is detected, the AMI ASIC will pull the /INT pin low and hold it low until the touch screen event registers (either column, row or both) are read. In contrast, the Xilinx FPGA will pulse /INT low for around 15 to 20 nanoseconds, then wait for the registers to be read before allowing another interrupt to be issued.

Both controllers appear to act upon the state of the /RESET line; that is, if /RESET is lowered, the interrupt flag is cleared and the touch screen controller reverts to a state of "no touch events detected".

The following scope traces (from my Tek TDS2024B) show the general form of the interrupt pulse:

Scope trace with auto-measured timing Scope trace with manually-derived timing

I suspect the 30cm length of ribbon cable and lack of decoupling is having an effect on this pulse (and the inverse-sinc shaped noise on the /INT line which was causing the Tek to mis-trigger)...

Example source code

  • PlanarEL160-80.zip -- C source code (MPLAB C18) for a test application using a Microchip PIC18F252.

References